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VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 2 OF 13
DOCUMENT REVISION HISTORY 1: DOCUMENT DATE DESCRIPTION REVISION FROM TO A 2004.07.19 First Release. Based on a.) Test Specification: VL-TS-MDLS161612D-XX, REV. D, 2004.05.18. b.) VL-QUA-012A, REV. R, 2004.03.20 (According to VL-QUA-012A, LCD size is middle because Unit Per Laminate=5 which is in the range of 2pcs to 6pcs/Laminate.)
CHANGED BY CHEN HUI JUAN
CHECKED BY DOS LEE
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 3 OF 13
CONTENTS
Page No. 1. 2. 3. 4. 4.1 4.2 5. 5.1 5.2 5.3 5.4 6. 7. GENERAL DESCRIPTION MECHANICAL SPECIFICATIONS INTERFACE SIGNALS ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS (Ta=25C) ENVIRONMENTAL CONDITION ELECTRICAL SPECIFICATIONS TYPICAL ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS TIMING DIAGRAM OF VDD AGAINST V0 CHARACTER GENERATOR ROM (NOVATEK STANDARD NT3881D-01) LCD COSMETIC CONDITIONS LABEL NOTE 4 4 6 7 7 7 8 8 9 11 12 13 13
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 4 OF 13
VARITRONIX LIMITED
Specification of LCD Module Type Item No.: MDLS161612D-09
1. General Description * * * * * 16 characters (5 x 8 dots) x 1 line STN Negative Blue Transmissive Dot Matrix LCD module. Viewing Angle: 6 O'clock direction. Driving duty: 1/16 Duty, 1/5 bias. `NOVATEK' NT3881DH-01/AI (die form) LCD Controller and Driver or equivalent Yellow-green LED04 backlight.
2.
Mechanical Specifications The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. Table 1 Parameter Outline dimensions Viewing area Display format Character size Character spacing Character pitch Dot size Dot spacing Dot pitch Weight Specifications 154.4(W) x 43.5(H) x 14.0 MAX.(D) 119.4(W) x 18.7(H) 16 characters x 1 line 5.90(W) x 12.70(H) (5 x 8 dots) 1.00(W) 6.90(W) 1.10(W) x 1.50(H) 0.10(W) x 0.10(H) 1.20(W) x 1.60(H) TBD Unit mm mm mm mm mm mm mm mm grams
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 5 OF 13
Figure 1: Outline Drawing
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 6 OF 13
3.
Interface signals Table 2
Pin No. 1 2 3 4
Symbol VSS VDD V0 RS
Description Ground(0V). Power supply for logic (+5V). Power supply for LCD driver. Register Select Input: "High" for Data register (for read and write) "Low" for Instruction register (for write), Busy flag, address counter (for read). Read/Write signal: "High" for Read mode. "Low" for Write mode. Enable. Start signal for data read /write. Data input/output (LSB). Data input/output. Data input/output. Data input/output. Data input/output. Data input/output. Data input/output. Data input/output (MSB). Anode of LED backlight. Cathode of LED backlight.
5 6 7 8 9 10 11 12 13 14 15 or A 16 or K
R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 LED(+) LED(-)
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 7 OF 13
4. 4.1
Absolute Maximum Ratings Electrical Maximum Ratings(Ta = 25 C) Table 3 Parameter Symbol Min. Max. Unit Power Supply voltage (Logic) VDD - VSS -0.3 +7.0 V Power Supply voltage (LCD drive) VLCD=VDD - V0 -0.3 +13.5 V Input voltage Vin -0.3 VDD +0.3 V Note: The modules may be destroyed if they are used beyond the absolute maximum ratings. All voltage values are referenced to VSS = 0V.
4.2
Environmental Condition Table 4 Operating Storage Temperature Temperature (Topr) (Tstg) Min. Max. Min. Max. 0C +50C -10C +60C 95% max. RH for Ta 40C < 95% RH for Ta > 40C Frequency: 10 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. Pulse duration : 11 ms 2 Peak acceleration: 981 m/s = 100g Number of shocks : 3 shocks in 3 mutually perpendicular axes.
Item Ambient Temperature Humidity Vibration (IEC 68-2-6) cells must be mounted on a suitable connector Shock (IEC 68-2-27) Half-sine pulse shape
Remark Dry no condensation 3 directions 3 directions
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 8 OF 13
5. 5.1
Electrical Specifications Typical Electrical Characteristics At Ta = 25 C, VDD = 5V5%, VSS=0V. Table 5 Parameter Supply voltage (Logic) Supply voltage (LCD) Input signal voltage for E,DB0-DB7,R/W,RS. Supply Current (Logic & LCD) Symbol VDD-VSS VLCD =VDD-V0 VIH VIL IDD Conditions VDD =5.0V, Note1. "H" level " L" level Character mode, Note 1 Checker board mode, Note 1 Character mode, Note 1 Checker board mode, Note 1 Forward current =170mA No. of LED chips =2x17=34 Note (1) : There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. Min. 4.75 4.1 2.2 -0.3 3.9 Typ. 5.00 4.5 1.3 2.0 0.9 0.9 4.1 Max. 5.25 4.9 VDD 0.8 2.0 3.0 1.4 1.4 4.3 Unit V V V V mA mA mA mA V
Supply Current (LCD)
I0
Supply Voltage of yellow-green LED04 backlight
VLED04
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 9 OF 13
5.2 Timing Specifications At Ta = 0 C To +50 C , VDD = +5V5%, VSS = 0V. Refer to Fig. 3, the bus timing diagram for write mode. Table 6 Parameter Enable cycle time Enable "High" level pulse width Enable rise time Enable fall time RS, R/W set-up time RS, R/W address hold time Data output delay Data hold time Symbol tCYCE tWHE tRE tFE tAS tAH tDS tDHR Min. 500 300 60 100 10 100 10 Max. 25 25 Unit ns ns ns ns ns ns ns ns Remarks
8-bit operation mode 4-bit operation mode
Refer to Fig. 4, the bus timing diagram for read mode . Table 7 Parameter Enable cycle time Enable "High" level pulse width Enable rise time Enable fall time RS, R/W set-up time RS, R/W address hold time Read data output delay Read data hold time Symbol tCYCE tWHE tRE tFE tAS tAH tRD tDHR Min. 500 300 60 100 10 20 Max. 25 25 190 Unit ns ns ns ns ns ns ns ns Remarks
8-bit operation mode 4-bit operation mode
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 10 OF 13
Figure 3: Bus write operation sequence (Writing data from MPU to NT3881D).
Figure 4: Bus read operation sequence (Reading out data from NT3881D to MPU).
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 11 OF 13
5.3
Timing Diagram of VDD against V0.
Power on sequence shall meet the requirement of Figure 5, the timing diagram of VDD against V0.
VDD
95%
LOGIC SUPPLY VOLTAGE 0V 50ms(typical)
V0
0V LCD SUPPLY VOLTAGE
Figure 5: Timing diagram of VDD against V0.
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 12 OF 13
5.4 Character Generator ROM (NOVATEK Standard NT3881D-01)
VL-FS-MDLS161612D-09 REV. A (MDLS161612D-LV-B-LED04G WITH CHROME BEZEL) JULY/2004 PAGE 13 OF 13
6.
LCD Cosmetic Conditions a.) Reference document follow VL-QUA-012A. b.) LCD size of the product is middle.
7.
Label Note a.) Identification labels will be stuck on the module without obstructing the viewing area of display.
"Varitronix Limited reserves the right to change this specification." FAX:(852) 2343-9555. URL:http://www.varitronix.com - END -

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